In many modern electronics applications, it is desirable to convert an analog signal to a digital value. For example, in a radio frequency (RF) transceiver, a received analog RF signal may be demodulated to an analog baseband signal which is then converted to a digital baseband signal for subsequent digital signal processing. Many electrical systems utilize analog-to-digital converters (ADCs) to convert an analog signal to a digital value. However, because of the finite nature of digital representation, quantization error (which is the difference between the actual analog value and quantized digital value due to rounding or truncation) is an imperfection inherent to the analog-to-digital conversion. In some ADCs, sigma-delta modulation (or alternatively, delta-sigma modulation) is used to reduce the effect of quantization error and improve signal-to-noise ratio (SNR). Sigma-delta modulation (alternatively referred to as delta-sigma modulation) adds or subtracts quantization error to a forward signal path using feedback loops and integrator circuits. The quantization error is oversampled at a frequency greater than the analog input signal frequency, thereby allowing it to be filtered at the integrators without noticeably impacting the signal.
Many systems utilize continuous-time sigma-delta modulators, that is, sigma-delta modulators constructed using continuous-time circuitry. Continuous-time sigma-delta modulators can be clocked at higher sampling frequencies which improves the performance of the sigma-delta modulator. In practice, however, high-speed sigma-delta modulators (generally sigma-delta modulators with sampling frequencies in the MHz range or higher) exhibit delay, referred to as excess loop delay, which can lead to instability and degrade performance (e.g., SNR) of the modulator. The loop delay results from, for example, the nonzero switching time of transistors and/or comparators utilized in the quantizer and/or digital-to-analog converter (DAC). As a result, there is a nonzero delay between a change at the quantizer output and the corresponding response at the output of the DACs in the main feedback path. The loop delay is further compounded by other factors, such as, for example, metastability in the comparators (or other components) and/or dynamic element matching. While the loop delay may be reduced with improvements to the hardware and/or electrical components, such improvements generally come at the cost of increased power consumption and larger area requirements, both of which are undesirable.
If the DAC in the feedback path of the modulator uses a return-to-zero (RZ) pulse scheme, the sigma-delta modulator may compensate for loop delay by adjusting the gain coefficients in the main feedback path. However, most systems utilize a no-return-to-zero (NRZ) pulse scheme for the main feedback path because NRZ pulses provide better immunity to clock jitter than RZ pulses. In the case of a NRZ pulse scheme, it is not possible to compensate for the loop delay by only adjusting the gain coefficients in the main feedback path.
Many prior art systems that utilize a NRZ pulse scheme attempt to mitigate the effects of loop delay by purposely inserting a constant delay in the main feedback path of the sigma-delta modulator and compensating for the constant delay with an additional term in the modulator transfer function. In some systems, an additional feedback path is inserted before the quantizer input and the gain coefficient of the DAC in the additional feedback path is adjusted to compensate for the constant delay. However, this increases the voltage swing at the output of the integrator preceding the quantizer. To offset this voltage swing, the overall gain of the modulator must be reduced, thereby reducing SNR. In addition, this approach creates a summing junction at the input of the quantizer. In order to process the high frequency signals present at the summing junction, the summing junction is often realized using an analog summer (e.g., a high-speed summing amplifier) which increases the power and area requirements for the modulator.
In order to avoid the use of a high-speed analog summer, some systems utilize digital differentiation to move the additional feedback path from the input of the quantizer to the input of the integrator that precedes the quantizer. While this eliminates the analog summer and reduces the voltage swing at the output of the integrator, the digital differentiation results in a bipolar RZ pulse at the input of the integrator. This causes the output of the integrator to move in the wrong direction during the first half of the clock period before switching direction in the second half of the clock period, resulting in a large slew rate requirement for the integrator. To satisfy the slew rate requirement, the integrator consumes additional power and area, which offsets the power and area saving from eliminating the analog summer. Other systems utilize proportional-integral (PI) compensation or other techniques which degrade the frequency response of the integrator and may lead to out-of-band peaking and other undesirable effects.